You have a section of what looks like it should be combinatorial logic in an always clk) block. Testbench wise I would set up a clock and reset like this : reg clk //Rising edge every 10 timestepsĪnd for the actual test something like : //The actual test #100 money = 2'b01 // putting 1st 25ps and 50ps i n second clock cycle ![]() #200 money = 2'b11 // putting 1 rs single time to g #200 money = 2'b10 // putting 75ps two times to get coffee #400 money = 2'b01 //putting 50ps two times to get coffee Money = 2'b00 // putting 25ps four times to get coffee Main dut( clk, rst, money, coffee, balance) Is clock frequency divider is necessary while doing the programme in fpga board to see output? It is working as expected when i programmed into fpga board.Im using Xilinx vivado 2015.2 tool and zynq board.Please help me to solve these issues //programmeĪ : if(money = 2'b00) // input money is 25psĮlse if(money = 2'b01) // input money is 50psĮlse if(money = 2'b10) // input money is 75ps Please help me to correct the test bench and my programme. ![]() ![]() Why this is happens? and also i didn't get output when using the test bench. simulation takes double clock pulse for output.(when i put 25 ps 8 times or 8 clock pulses is required for getting output. If more than 1rs is inserted, the balance will be returned. I have written a verilog code for a simple coffee vending machine with inputs
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